Seminar Series:




A blood donation camp was organized on Saturday, 19th March, at Arpan Voluntary Blood Bank, Nagpur by students of Centre for VLSI and Nanotechnology. Arpan Blood Bank is Nagpur Municipal Corporation's hi-tech blood bank at Indira Gandhi Rugnalaya. It operates on no-profit basis. Patients suffering from diseases like thalassemia, sickle cell anaemia etc. are given blood at nominal rate as compared to the private blood banks.


It began at around 11.45 am and continued up to 3 pm, with a steady stream of donors including the post graduate and doctoral students. Pick up and drop facility was available from the college to the Blood Bank from their side. The students were excited and happy to be able to contribute for the noble cause.


The potential donors were first counselled for filling the donation form followed by medical check-up for blood tests and body weight. Depending on reports, donors were selected and sent to the Donor Room for the same. It was observed that O+ blood donors were maximum. The students were allowed to rest for 5-10 mins to recuperate and then were provided with refreshments like water, fruit juice, eatables including glucose biscuits and savoury snacks. It was good to see more people than registered at the venue.


The donors were handed certificate of recognition and t-shirt. They also got a card where blood will be available at concessional rate for next one year. A momento was handed over for the department. The students were also encouraged to donate blood after every 3 months and spread the awareness among other people as well.


Throughout the camp, there were smiles on everyone’s face and a determination to keep the good work going for time to come !!!



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Prof. Subir Roy, IIIT Bangalore February 25-27, 2016


Prof. Subir Roy


Department of Electronic System design


IIIT Bangalore


Feb 25, 2016 Introduction to VerificationDuration: 2 hours


Feb 26, 2016 Formal Verification Duration: 2 hours


Feb 27, 2016 Formal Verification Duration: 3 hours


Functional verification of complex SOCs, such as those in smartphones, with innumerous features and functionalities, is an exceedingly difficult task. While multiple approaches are taken to ensure that no design bugs are found on Silicon, the route taken to verify the design from a hardware perspective, with various IPs being integrated to realize an SOC, is primarily based on simulation, given its ability to scale with the design size. It is well known that simulation is largely inadequate in exercising various corner case functional behaviour, regardless whether the simulation is based on manually designed test-cases or based on constrained random generation. This is primarily due to the inadequacy of specifications available at the micro-architectural level of design details. These specifications can help design test cases to capture corner case behavioural scenarios arising out of the intricate interactions that take place between different IPs and design blocks within an SOC. These factors contribute to a lower confidence in the functional verification process, Silicon re-spins and costly overruns in schedule. Automated assertion synthesis based verification can help accelerate verification closure by adding specifications at the micro-architectural level in an implementation through white box assertions and functional coverage properties, to capture formally the design intent of a block in terms of the behaviour of its implementation signals. These properties improve observability of design behaviour and enable detection of functional coverage holes. Running these assertions in either a formal tool or a simulator can enable verification engineers to ascertain the quality of the RTL.

Prof. Madhav P. Desai, IIT Bombay February 12-13, 2016


Prof. Madhav P. Desai


Department of Electrical Engineering


IIT Bombay


Feb 12, 2016 Digital System Design (System to RTL design) Duration: 2 hours


Feb 13, 2016 Simulation Acceleration through FPGA Duration: 1.5 hours


Q & A, Demo Duration: 3.5 hours




With the decrease in feature size to the sub-100nm range, the available capacity of an integrated circuit has increased substantially. However the design process has become a bottleneck since description/verification using VHDL/Verilog is still tedious. In this context, techniques to convert algorithmic and behavioural descriptions of systems into synthesizable hardware descriptions is being worked on. The key concepts behind this approach was described and the AHIR toolset and the algorithmic assembly language was introduced with a few illustrations.


Date: 5 February 2016 Duration: 2 hours




Comsol Multiphysics India organised a seminar focusing on the capabilities ofCOMSOLMultiphysics 5.2 and Application Builder focussing on the following points:


  • Fundamental modeling steps inCOMSOLMultiphysics 5.2
  • Capabilities ofCOMSOLwithin application specific area (with a live multiphysics simulation example)

Set up and solving a simulation through a hands-on exercise


Center for VLSI and Nanotechnology and Antenna Propagation and Electronic Devices (AP-ED) Chapter of IEEE Bombay section celebrated the event for Centenary Celebration of Dr. Claude E. Shannon by organising seminars and workshop by renowned faculties worldwide.

Dr. Claude E. Shannon:

Dr. Claude E. Shannon, born on April 30, 1916 Mathematician and Engineer, is known as the Father of the Information Age or Father of the Digital Revolution. He is one of the few men that get mentioned in the same sentence as Einstein. He would be on the Mount Rushmore of High Tech if commissioned. The digital world originated in his paper considered to be the Magna Carta of the information age, “A Mathematical Theory of Information”, written at the legendary Bell Labs in 1948. He is revered by the academic and research communities in Electrical Engineering, Computer Science and Mathematics. Shannon's equations and mathematical ideas led to digital signal processing, data compression, data encryption, networking, data storage and the modern digital world. His ideas were the genesis for the brilliant engineers, scientists and entrepreneurs that would create Intel, Cisco, Qualcomm, Apple, Microsoft, Google and the technology they gave the world. It's a list that is never ending and will keep going.








The AJIT processor project

Seminar:The AJIT processor project at IIT Bombay


Prof. Madhav P. Desai

Department of Electrical Engineering

IIT Bombay

Feb 12, 2016 Duration: 1.5 hours


The AJIT processor implements the IEEE 1754 draft standard ISA (Sparc V8) and has been developed at IITB over the past 18 months. In designing this processor, extensive use of algorithmic descriptions of the processor was made. The processor CPU core runs on an FPGA and a Linux port to this processor was also completed. The processor architecture itself uses an elastic pipeline concept whose functional correctness is independent of the delays in individual pipeline stages. The talk describes the architecture and design methodology used during the design process, and the future directions of research and development around this processor was outlined.

viciLogic and viciLab

Workshop: viciLogic and viciLab Workshop


Dr. Fearghal Morgan

National University of Ireland, Galway

Feb 24, 2016 Duration: 1 day


The workshop was divided into two halves viz. seminar and hands-on training. The seminar elaborated about viciLogic as a platform for effective pedagogical solution for online technology enhanced learning, assessment and prototyping of digital logic and computer architecture systems. It provides direct access and interaction with an array of Reconfigurable Computing (RC) digital logic hardware in the Cloud using only an internet connection. In the second half of the workshop, he demonstrated some examples on remote FPGA boards and also gave a hands-on to the participants. He discussed various issues in digital technology and their probable solutions.

Profiling tools for Embedded Systems

Seminar: Profiling tools for Embedded Systems

Prof. Subir Roy

Department of Electronic System design

IIIT Bangalore

Feb 25, 2016 Duration: 1.5 hours


Modern embedded systems are typically implemented using both programmable processors and application specific hardware in order to meet real time design goals, besides other metrics, such as, performance, area and cost. The availability of programmable processors and application specific hardware enables an application architect to partition the execution of the given application code (specified in some high-level language) optimally; so as to execute as large a portion of it, which is timing or performance non-critical, on the processor to lower implementation cost and the timing critical rest, in expensive application specific digital hardware, implemented either as an ASIC or programmed into a FPGA. Profiling tools enables this optimal partitioning by monitoring the execution of the application code running on a processor and capturing different characteristics of the program execution. One of the important aspect that needs to be profiled is the cost of executing functions or subroutines, in terms of both the computational cost, as well as, the communication cost. The talk presents an efficient, non-intrusive FPGA-based application profiler to address this aspect. Unlike other profilers, the proposed approach does not involve any modification at the hardware level in the actual implementation of any chosen processor and neither is there any need to re-synthesize the profiler to profile any new application.